The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Aug. 09, 2000
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A process for forming an implanted ESD region, and for forming metal silicide blocking regions, using the same photolithographic mask for definition of these regions, has been developed. The process features the formation of an implanted ESD region, defined by a photoresist shape which in turn had been formed via exposure of a negative photoresist layer, using a specific photolithographic mask. Metal silicide regions are subsequently formed on regions of a semiconductor substrate, exposed in openings in an insulator layer, with the openings in the insulator layer defined via a photoresist shape, which in turn had been formed via exposure of a positive photoresist layer, using the same photolithographic mask previously used for definition of the implanted ESD region. In this invention we use only one photolithographic mask in the CMOS process to fabricate an ESD device having ESD implanted and metal silicide blocking regions, which can sustain higher ESD stress.