Method and apparatus for detecting intercell defects in a memory device

Abstract

A method for identifying intercell defects in a memory device activates a plurality of spaced-apart rows simultaneously. Each of the rows includes cells that are written to logic states corresponding to high voltages. Cells in rows adjacent to the activated rows are written to logic states corresponding to low voltages. After the rows are activated, a testing interval passes to allow charge from cells of the activated rows to leak to adjacent cells through any stringers or other defects. In a device according to the invention, a variable voltage level circuit is incorporated in a precharge and equalization circuit to allow both inverting and non-inverting digit lines of the memory array to be set at the same voltage levels. Because the inverting and non-inverting digit lines are held at the same voltage levels, the number of word lines that can be activated for testing is increased, thereby reducing the overall time for testing. In one embodiment of the method according to the invention, the memory array is written to a checkerboard pattern and every fourth word line is activated during testing. Because every fourth word line contains cells having a high voltage and the corresponding digit lines are also at high voltages, the load on the digit lines is small. Consequently, sense amplifiers coupled to the digit lines can maintain high voltages on the digit lines to replace any charge lost due to defects.