The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2002
Filed:
Jan. 23, 2001
Wen Chuan Chen, Chupei, Hsinchu Hsien, TW;
Kuo Feng Peng, Chupei, Hsinchu Hsien, TW;
Jichen Wu, Chupei, Hsinchu Hsien, TW;
Chia Jung Chang, Chupei, Hsinchu Hsien, TW;
Other;
Abstract
The structure of stacked integrated circuits includes a substrate, a lower integrated circuit, a plurality of wirings, an adhesive layer, and an upper integrated circuit. The substrate has a first surface formed with signal input terminals, and a second surface formed with signal output terminals. The lower integrated circuit has a first surface and a second surface. The first surface is adhered to the first surface of the substrate while the second surface is formed with a plurality of bonding pads. The wirings have first ends and second ends. The first ends are electrically connected to the bonding pads of the lower integrated circuit while the second ends are electrically connected to the signal input terminals of the substrate. The adhesive layer is coated on the second surface of the lower integrated circuit and includes adhesive agent and filling elements. The upper integrated circuit is stacked above the second surface of the lower integrated circuit with the adhesive layer inserted between the upper and lower integrated circuit. The lower integrated circuit is adhered to the upper integrated circuit by the adhesive agent. A predetermined gap is formed between the lower and upper integrated circuit by the filling elements. According to this structure, the wirings located under the lower integrated circuit are free from being pressed and damaged by the upper integrated circuit when stacking a plurality of integrated circuits. Thus, the stacking processes can be facilitated and the manufacturing costs can also be lowered.