The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2002

Filed:

Feb. 09, 2001
Applicant:
Inventors:

Ji-Wei Liou, Hsin-Chu, TW;

Chih-Jen Huang, Hsin-Chu, TW;

Pao-Chuan Lin, Yun-Lin Hsien, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method of fabricating a trenched flash memory cell is provided. A plurality of shallow trench isolation structures are formed to enclose at least an active area in a silicon substrate. A doped region is formed in the silicon substrate, followed by the deposition of an isolation layer on the silicon substrate. A first photo and etching process (PEP) is performed to form two trenches within the active area. A tunnel oxide layer, a floating gate, and ONO dielectric layer are formed in the trenches, respectively. A doped polysilicon layer is then formed on the silicon substrate to fill the trenches, followed by the removal of a portion of the doped polysilicon layer to form two controlling gates in the active area. Next, a self-alignment common source is formed between the two controlling gates and a plurality of spacers are formed on either side of each controlling gate. Finally, a silicide layer is formed on the surfaces of the controlling gates and the common source.


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