The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2002
Filed:
Apr. 11, 2000
Applicant:
Inventors:
Jeffrey P. Gambino, Gaylordsville, CT (US);
Gary B. Bronner, Stormville, NY (US);
David E. Kotecki, Hopewell Junction, NY (US);
Carl J. Radens, LaGrangeville, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1119 ;
Abstract
A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.