The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2002
Filed:
Dec. 03, 1998
Applicant:
Inventors:
Chin-Yu Tsai, HsinChu Hsien, TW;
Taylor R. Efland, Richardson, TX (US);
Sameer Pendharkar, Richardson, TX (US);
John P. Erdeljac, Plano, TX (US);
Jozef Mitros, Richardson, TX (US);
Jeffrey P. Smith, Plano, TX (US);
Louis N. Hutter, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 3/1113 ;
U.S. Cl.
CPC ...
H01L 3/1113 ;
Abstract
An LDMOS device ( ) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells ( ). The Dwell ( ) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region ( ), which permits the n-type region of the Dwell to diffuse under the gate region ( ) an sufficient distance to eliminate misalignment effects.