The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2002

Filed:

Aug. 27, 1998
Applicant:
Inventors:

Izak Bencuya, Saratoga, CA (US);

Maria Christina B. Estacio, Bacayan, PH;

Steven P. Sapp, Felton, CA (US);

Consuelo N. Tangpuz, Lapulapu, PH;

Gilmore S. Baje, Lapulapu, PH;

Rey D. Maligro, Cordova, PH;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.


Find Patent Forward Citations

Bencuya, Izak. (2002). Low resistance package for semiconductor devices (U.S. Patent No. 6423623). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6423623

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…