The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2002
Filed:
Dec. 23, 1998
Gregory S. Mathews, Santa Clara, CA (US);
Dean A. Mulla, San Jose, CA (US);
John Wai Cheong Fu, Saratoga, CA (US);
Stuart E. Sailer, Campbell, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB memory having a plurality of entries and a second-level TLB memory operatively coupled to the first level TLB memory. The second-level TLB memory also has a plurality of entries. Entries are placed in the TLB and TLB structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.