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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6413824 B1

PDFFull Text
Date of Patent:
Jul. 02, 2002

Filed:

Jun. 08, 2000

Method to partially or completely suppress pocket implant in selective circuit elements with no additional mask in a cmos flow where separate masking steps are used for the drain extension implants for the low voltage and high voltage transistors

Applicant:
Inventors:

Amitava Chatterjee, Plano, TX (US);

Alec J. Morton, Plano, TX (US);

Mark S. Rodder, University Park, TX (US);

Taylor R. Efland, Richardson, TX (US);

Chin-Yu Tsai, Plano, TX (US);

James R. Hellums, Plano, TX (US);

Assignee:

Texas Instruments Incorporated, Dallas, TX (US);

Attorney:
Primary Examiner:

Long Pham

Int. Cl.
CPC ...
H01L 2/18234 ;
U.S. Cl.
CPC ...
H01L 2/18234 ;
Abstract

High performance digital transistors ( ) and analog transistors ( ) are formed at the same time. The digital transistors ( ) include pocket regions ( ) for optimum performance. These pocket regions ( ) are partially or completely suppressed from at least the drain side of the analog transistors ( ) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors ( ).

Find Patent Forward Citations

Chatterjee, Amitava. (2002). Method to partially or completely suppress pocket implant in selective circuit elements with no additional mask in a cmos flow where separate masking steps are used for the drain extension implants for the low voltage and high voltage transistors (U.S. Patent No. 6413824). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6413824

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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