The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2002
Filed:
Oct. 23, 2000
Chenming Hu, Alamo, CA (US);
Tsu-Jae King, Fremont, CA (US);
Vivek Subramanian, Redwood City, CA (US);
Leland Chang, Berkeley, CA (US);
Xuejue Huang, Albany, CA (US);
Yang-Kyu Choi, Albany, CA (US);
Jakub Tadeusz Kedzierski, Hayward, CA (US);
Nick Lindert, Berkeley, CA (US);
Jeffrey Bokor, Oakland, CA (US);
Wen-Chin Lee, Beaverton, OR (US);
The Regents of the University of California, Oakland, CA (US);
Abstract
A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.