Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions

Abstract

A method for making borderless contacts to source/drain areas that overlap the STI is achieved. The method reduces contact shorts between the source/drain and the substrate, and eliminates erosion of the gate oxide to prevent gate/drain shorts. The method involves forming trenches in a silicon substrate, which are filled with a silicon oxide (SiO ) and etched back to form STI surrounding and electrically isolating device areas. The STI is essentially planar with the substrate surface. A gate oxide is formed on the device areas and a polysilicon or polycide layer is patterned to form FET gate electrodes. A first silicon nitride (Si N ) layer is deposited and etched back to form sidewall spacers on the gate electrodes. The STI is recessed using a dip etch. A thin stress-release oxide is formed and a second Si N layer is deposited and etched back to form visors (protective coverings) on the exposed sidewalls of the trench. An interlevel dielectric is deposited and borderless contact openings that extend over the STI can now be etched to the active device areas to provide improved circuit density. When metal plugs are formed in the contact openings, the visor protects the source/drain contacts and the underlying substrate from electrical shorting.