On-chip circuits for high speed memory testing with a slow memory tester

Abstract

A memory system on a semiconductor body is tested by testing components formed on the semiconductor body. A programmable clock signal generator receives an external clock signal and selectively generates an output clock signal having a frequency at a predetermined multiple of the received external clock signal. A counter receives the output clock signal from the clock signal generator and generates output signals having a cyclical binary count up to the predetermined multiple of the received external clock signal. Memory locations in a programmable look-up memory store separate commands for testing the memory system. The programmable look-up memory receives each of selective remotely generated binary encoded address signals to access a separate predetermined look-up memory section, and the binary output signals from the counter for sequentially accessing separate memory locations within the separate predetermined look-up memory section.