Method for making deep trench capacitors for drams with reduced faceting at the substrate edge and providing a more uniform pad si3n4layer across the substrate

Abstract

A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si N ) uniformity for increasing process yields. The method utilizes a thicker pad Si N as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si N layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si N layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si N layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si N layer to provide a more reliable structure for further processing.