The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2002
Filed:
Oct. 18, 2000
Michael E. Barsky, Sherman Oaks, CA (US);
Richard Lai, Redondo Beach, CA (US);
Ronald W. Grundbacher, Hermosa Beach, CA (US);
Rosie M. Dia, Carson, CA (US);
Yaochung Chen, Rancho Palos Verdes, CA (US);
TRW Inc., Redondo Beach, CA (US);
Abstract
A method for determining the etch depth of a gate recess ( ) in an InP based FET device ( ). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.