Integrated circuit tester having a program status memory

Abstract

An integrated circuit (IC) tester employs a pattern generator including an instruction processor executing an algorithmic program stored in a program memory. The program defines a sequence of vectors defining test activities to be carried out during successive cycles of a test on an IC. In the course of executing the program, the instruction processor stores in various registers and counters “program status” data that the processor uses to keep track of program execution. The status data may include, for example, the current program memory address, loop and repeat counts, return addresses and the like. The pattern generator also includes a random access “program status” memory for storing a selected portion of the program status data at selected points during a test. The algorithmic program defining the vectors to be produced for each cycle of the test also selects a test event (such as a DUT failure) that is to trigger program status data storage during any test cycle, selects the particular status data to be stored in response to the test event, and selects the status memory address at which the data is to be stored. Test analysis software may read the program status data out of the program status memory following the test and use it to determine the status of program execution at the time the triggering events occurred.