The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2002

Filed:

Oct. 10, 2000
Applicant:
Inventor:

Chia-Yu Hung, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/334 ;
U.S. Cl.
CPC ...
H01L 2/334 ;
Abstract

A stacked integrated circuit structure, in which main package bodies of a plurality of integrated circuits are stacked on each other. Connections between leads of the stacked integrated circuits are made by means of a stacking substrate. Therein, each of two surfaces of the stacking substrate has a plurality of terminals electrically connected to corresponding terminals. The stacking substrate includes a plurality of through vias as well, which connect to the corresponding terminals of the two surfaces. For two stacked integrated circuits, a hole can be defined in the stacking substrate, which housed the main package body of one of the two stacked integrated circuits, or by means of a plurality of separated substrates arranged around the perimeter of the main package body of one of the two stacked integrated circuits, so that the thickness of the stacked integrated circuits can be reduced.


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