The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2002
Filed:
Apr. 24, 2000
Tzu-Shih Yen, Hsin-Chu, TW;
Erik S. Jeng, Hsin-Chu, TW;
I-Ping Lee, Hsin-Chu, TW;
Eddy Chiang, Hsin-Chu, TW;
Vanguard International Semiconductor Corporation, Hsin-chu, TW;
Abstract
A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen. The method may also be employed in general for etching silicon oxide layers in the presence of silicon nitride layers. Similarly, the method may also in general be employed in removing fluorocarbon polymer residue layers from integrated circuit layers including but not limited to silicon oxide layers and silicon nitride layers.