The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2002
Filed:
Nov. 06, 2000
William D. Higdon, Greentown, IN (US);
Frank Stepniak, Noblesville, IN (US);
Delphi Technologies, Inc., Troy, MI (US);
Abstract
A solder bumping method and structure for fine solder bump pitches. The method makes use of a semiconductor device having an input/output pad whose surface is provided with a solderable metal layer that serves as the UBM of the solder bump. A sacrificial layer is formed on the surface of the device to surround the metal layer. A plating seed layer is then formed on the metal layer and the surrounding surface of the sacrificial layer, after which a mask is formed on the seed layer and a via is defined in the mask to expose portions of the seed layer overlying the metal layer and the sacrificial layer. A solder material is deposited on the seed layer exposed within the via. The mask is then removed, followed by removal of a portion of the seed layer that is not covered by the solder material, leaving intact that portion of the seed layer beneath the solder material. The sacrificial layer is then removed, including that portion of the sacrificial layer underlying the seed layer, such that a gap is formed between the substrate and the remaining seed layer. Finally, the solder material is reflowed to form a solder bump into which the remaining seed layer is dissolved.