The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2002
Filed:
Jul. 14, 1998
Richard Ernest Demaray, Portola Valley, CA (US);
Chandra Deshpandey, Fremont, CA (US);
Rajiv Gopal Pethe, Sunnyvale, CA (US);
Applied Komatsu Technlology, Inc., Tokyo, JP;
Abstract
Thin semiconductor films or layers having a pre-selected degree of crystallinity, from amorphous material to poly-crystalline material, can be obtained by selecting an appropriate aspect ratio for a collimator used during a sputtering process. The orientation of the deposited film also can be tailored by selection of the collimator aspect ratio. Sputtered collimation permits highly crystalline films to be formed at temperatures significantly below the annealing temperature of the sputtered material. Thus, required fabrication steps and increase the throughput of the use of low temperatures allows films of substantially greater crystallinity and carrier mobility to be fabricated on glass and other low temperature substrates. Additionally, thin semiconductor Trapped charge defects also can be reduced by grounding the collimator to provide electrical isolation between the charged plasma particles and the substrate on which the sputtered layer is to be formed. Dielectric films having a thickness as small as several hundred Å can be formed to fabricate high transconductance devices with high breakdown strengths. improved electrically active interfaces, such as a rectifying junction between a semiconductor layer and a dielectric layer or an ohmic junction between intrinsic and doped semiconductor materials.