Method of forming mosfet gate electrodes having reduced depletion region growth sensitivity to applied electric field

Abstract

A method of fabricating a FET having a gate electrode with reduced susceptibility to the carrier depletion effect, includes increasing the amount of n-type dopant in the gate electrode of an n-channel FET. In one embodiment of the present invention, an integrated circuit including NFETs and PFETs is produced with increased n-type doping in the n-channel FET gate electrodes without the use of additional photomasking operations. Prior to polysilicon patterning, a phosphorus doped silica glass (PSG) is deposited over the polysilicon. Subsequent to patterning of the polysilicon, NFET areas are masked, and exposed PFET areas subjected to source/drain extension implant operations. During this sequence, the PSG is removed from PFET areas but remains in the NFET areas. An anneal is performed to drive the phosphorus from the PSG into the NFET gate electrodes. NFET source/drain extensions are formed, and conventional MOSFET processing operations may then be performed to complete the integrated circuit. Embodiments of the present invention achieve the desired higher levels of doping without an additional masking operation, thereby achieving the desired electrical characteristics at a lower manufacturing cost.