Method of fabricating an electronic component and apparatus used therefor

Abstract

The present invention provides a method of fabricating an electronic component, using a tool for pressing a chip against a substrate and heating the same, connecting a chip electrode and a substrate electrode together via a bump, placing the substrate in alignment with a die alignment plane for an upper die and a lower die, clamping the upper die and the lower die to form a cavity and exhausting the cavity via an exhaust hole to evacuate the same, and injecting melted resin into the cavity and curing the melted resin to provide sealing resin. Then, in a predetermined ambient at a predetermined temperature the substrate is pressed against a test board and a predetermined electrical signal is applied from the test board via an external electrode to the chip to test an operation of an electronic component configured on a unit region of the substrate and the chip. Thereafter, cutting along a virtual line completes the electronic component. Thus, a plurality of chips can be resin-sealed collectively with high precision and a plurality of electronic components can be burnt in. As a result, in mounting the chip to the substrate, sealing the same with resin and burning in the same to provide an electronic component, the electronic component can be efficiently fabricated, with the sealing resin having a dimension with high precision.