The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2002

Filed:

Aug. 11, 1999
Applicant:
Inventors:

Richard J. Huang, Cupertino, CA (US);

Lewis Shen, Cupertino, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ;
U.S. Cl.
CPC ...
H01L 2/13205 ;
Abstract

A thermally grown oxide buffer layer is formed on a silicon layer prior to depositing an ARC thereon, thereby preventing damage to the silicon layer during ARC removal. Embodiments include thermally growing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by thermal oxidation at a temperature of about 800° C. to about 900° C. in an atmosphere comprising oxygen or steam. A silicon oxynitride or silicon-rich silicon nitride ARC is then formed on the thermally grown protective silicon oxide buffer layer and a photoresist layer is formed on the ARC. The photoresist layer is patterned to form a mask and the underlying silicon layer etched to form a conductive feature, e.g., gate electrode. The photoresist mask is then removed and the ARC is stripped with hot phosphoric acid or by dry etching, while the thermally grown silicon oxide buffer layer protects the underlying silicon layer from damage.


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