The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2002

Filed:

Apr. 11, 2000
Applicant:
Inventors:

Hamid Norrbakhsh, Fremont, CA (US);

Mike Welch, Livermore, CA (US);

Paul Luscher, Sunnyvale, CA (US);

Siamak Salimian, Sunnyvale, CA (US);

Brad Mays, San Jose, CA (US);

Assignee:

Applied Materials Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05B 1/00 ; A21B 2/00 ; F27B 5/06 ; G01K 1/00 ;
U.S. Cl.
CPC ...
H05B 1/00 ; A21B 2/00 ; F27B 5/06 ; G01K 1/00 ;
Abstract

The invention solves the problem of continuously monitoring wafer temperature during processing using an optical or fluoro-optical temperature sensor including an optical fiber having an end next to and facing the backside of the wafer. This optical fiber is accommodated without disturbing plasma processing by providing in one of the wafer lift pins an axial void through which the optical fiber passes. The end of the fiber facing the wafer backside is coincident with the end of the hollow lift pin. The other end is coupled via an “external” optical fiber to temperature probe electronics external of the reactor chamber. The invention uses direct wafer temperature measurements with a test wafer to establish a data base of wafer temperature behavior as a function of coolant pressure and a data base of wafer temperature behavior as a function of wafer support or “puck” temperature. These data bases are then employed during processing of a production wafer to control coolant pressure in such a manner as to minimize wafer temperature deviation from the desired temperature.


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