Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers

Abstract

A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.