The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2001
Filed:
Jan. 27, 2000
Daniel Sobek, Portola Valley, CA (US);
Timothy Thurgate, Sunnyvale, CA (US);
Carl Robert Huster, Sunnyvale, CA (US);
Masaaki Higashitani, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
The method of fabricating the semi-conductor device includes forming a center dielectric region on a substrate. The center dielectric region has a first thickness and the substrate includes a first conductive material. Then, a first plurality of spacers is formed near the center dielectric region. A second conductive material is implanted into the substrate using the first plurality of spacers for alignment. The second conductive material form sources/drains the first plurality of spacers are then removed and a dielectric layer is formed over the substrate and the source/drain regions. The dielectric layer has a second thickness that is less than the first thickness. A second plurality of spacers is formed near the center dielectric region. The second plurality of spacers are conductive and have a third thickness that is substantially equal to the difference of the first and second thickness'. A gate dielectric layer is formed over the substrate, center dielectric region, and second plurality of spacers. Finally, a control gate layer is formed over the gate dielectric layer.