The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6323073 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 27, 2001

Filed:

Jan. 19, 2001
Applicant:
Inventors:

Wen-Kuan Yeh, Chu-Pei, TW;

Hua-Chou Tseng, Hsin-Chu, TW;

Jiann Liu, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1338 ;
U.S. Cl.
CPC ...
H01L 2/1338 ;
Abstract

An SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A shallow trench isolation structure is formed on the silicon layer. The STI structure passes through to the dielectric layer. A thermal diffusion process is performed to drive dopants into a first region of the silicon layer so as to form an N-well or P-well doped region. Next, a thermal diffusion process is performed to drive dopants into a second region of the silicon layer so as to form a P-well or N-well doped region. Finally, an epitaxy layer, having a thickness of about 200 angstroms, is grown on the surface of the silicon layer by way of a molecular-beam epitaxy (MBE) growth process, a liquid-phase epitaxy (LPE) growth process, or a vapor-phase epitaxy (VPE) growth process.


Find Patent Forward Citations

Yeh, Wen-Kuan. (2001). Method for forming doped regions on an soi device (U.S. Patent No. 6323073). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6323073

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