The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2001
Filed:
Apr. 14, 1999
Salman Akram, Boise, ID (US);
John R. C. Futrell, Boise, ID (US);
Steven M. McDonald, Meridan, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Disclosed herein is the formation of a ball grid array testing receiver that is scalable for design consideration of miniaturization. A dielectric layer is formed upon a substrate that is substantially conformal to the upper surface of the substrate. A patterned masking layer is formed upon the dielectric layer and a subsequent etch forms a depression within the substrate and forms a ledge on the surface of the substrate that is adjacent to the depression. After formation of the ledge, a metal layer is formed continuously on the ledge and within the depression. Following the formation of the metal layer, a masking layer is formed upon the metal layer. The masking layer is patterned so as to form a desired arrangement of metal lines by etching the underlying metal layer. The formation of the ledge enables the masking layer to resist formation of a breach between the surface of the substrate and the depression. As such, metal lines are formed so as to extend into the depression without a breach that would otherwise leave an open circuit during attempted use.