The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2001

Filed:

Dec. 28, 1999
Applicant:
Inventors:

Chien-Ping Huang, Hsinchu Hsien, TW;

Lian-Cherng Chiang, Taichung, TW;

Wen-Ta Tsai, Taichung Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/3495 ;
U.S. Cl.
CPC ...
H01L 2/3495 ;
Abstract

A dual-chip integrated circuit (IC) package is provided, which is characterized in the use of a an extending portion formed from the leads of a leadframe to provide firm support to the bonding pads on the chips. The dual-chip integrated circuit package utilizes a leadframe having a first leads and a second leads, with a spacing being defined between the first and second leads; and the first leads is extended toward the spacing to form the extending portion at a downset position with respect to the second plane where the leadframe positions leads. A first integrated circuit chip is mounted on the extending portion in such a manner that the front side thereof is attached to the extending portion; and a second integrated circuit chip is attached to the first integrated circuit chip in a back-to-back manner. The bonding pads on the two integrated circuit chips are electrically connected to the first and second leads via a plurality of bonding wires. The use of the extending portion for the attachment of the two integrated circuit chips can help prevent delamination of the chips and can provide firm support to the bonding pads on the chips so that the chips can be prevented from being cracked during the wire-bonding process. The manufactured integrated circuit package can therefore be more assured in reliability and quality.


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