The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2001

Filed:

Oct. 12, 1999
Applicant:
Inventors:

Amitava Chatterjee, Plano, TX (US);

Wei William Lee, Plano, TX (US);

Greg A. Hames, Dallas, TX (US);

Quzhi He, Plano, TX (US);

Iqbal Ali, San Jose, CA (US);

Maureen A. Hanratty, Dallas, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ;
U.S. Cl.
CPC ...
H01L 2/976 ;
Abstract

A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (,) having a channel region (,). A gate insulation (,) may be adjacent the channel region (,) of the semiconductor substrate (,). A gate (,) may be formed adjacent the gate insulation (,). A sidewall insulation body (,) may be formed adjacent a portion of the gate (,). The sidewall insulation body (,) is comprised of a silicon oxynitride material. An epitaxial layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the semiconductor substrate (,) substantially outward of the channel region (,). A buffer layer (,) may be formed adjacent a portion of the sidewall insulation body (,) and adjacent the epitaxial layer (,).


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