The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2001
Filed:
Nov. 05, 1998
Shou-Zen Chang, Hsin-Chu, TW;
Chao-Chieh Tsai, Taichung, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-chu, TW;
Abstract
The present invention provides a method for fabricating elevated and drain structures on a substrate. A first insulating layer is formed over a silicon substrate. A first barrier layer is formed over the first insulating layer. The first barrier layer, the first insulating layer and the substrate are patterned to form a trench. Ions are implanted into the substrate in the trench. A gate oxide layer is formed on the substrate in the trench. A polysilicon layer is deposited over the gate oxide layer and the barrier layer. The polysilicon layer is planarized using a chemical mechanical polishing process (CMP) stopping on the barrier layer to form a novel recessed gate. The barrier layer and the first insulating layer are removed. Lightly doped source/drain regions (LDD) are formed adjacent to the recessed gate. Spacers are formed on the sidewalls of the recessed gate. Source and drain regions are formed adjacent to the spacers. Salicide layers are formed on the source and drain regions and on the top of the recessed gate.