Chip scale package

Abstract

The present invention discloses a chip scale package. According to this invention, a lead frame,is bonded with an adhesive,to a bottom face of a semiconductor chip,. An inner lead,of the lead frame,is connected to a pad,of the semiconductor chip with a metal wire,, and thickness of the inner lead,is equal to an original thickness of the lead frame,. An outer lead,of the lead frame,is formed by partially etching a bottom face of the lead frame,. The entire resultant is encapsulated with a molding compound,such that the outer lead,is exposed therefrom, especially there is formed a downward protruding portion,at the molding compound,in the lower inner lead portion,. This protruding portion raises the margin controlling the bonding height during the wire-bonding process such that the metal wire,is not exposed from the molding compound,. Furthermore, the outer leads,at both sides where no solder balls are mounted on, are exposed from the molding compound,. The outer leads,at both sides being exposed from the molding compound,act for dissipating outwardly heat that is transmitted from the semiconductor chip,to the lead frame,. A solder ball,is mounted at the inside of the outer lead,exposed from the molding compound