The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2001

Filed:

Nov. 23, 1999
Applicant:
Inventors:

Philippe Coronel, Massy, FR;

Edith Lattard, Trets, FR;

Renzo Maccagnan, Villabe, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/18242 ;
Abstract

A conventional initial deep trench structure consists of a patterned Si,N,pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO,collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO,is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO,is etched at least 6 times faster than the Si,N,(stopping on the Si,N,pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6× the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages. Next, N-type dopant is implanted in the upper portion of the silicon substrate to create a doped region. The trench is filled with a layer of doped polysilicon (POLY2) which is planarized by chemical-mechanical polishing down to approximately the Si,N,pad layer surface and finally recessed down to a depth level substantially coplanar with the silicon surface substrate to create a POLY2 stud. The buried strap is formed by the doped region and POLY2 stud. The above method presents significant advantages in terms of product reliability, throughput improvements and process flow simplification.


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