The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2001
Filed:
Aug. 26, 1999
Ku Chul Joung, Chungcheongbuk-do, KR;
Wouns Yang, Chungcheongbuk-do, KR;
Kun Sik Park, Taejon-kwangyoksi, KR;
Hyundai Electronics Industries Co., Ltd., Kyoungki-do, KR;
Abstract
A method for fabricating a semiconductor memory, in which a resistive layer is formed of a material identical to a material of a cell plug layer at a time of formation of the cell plug layer. In addition, a contact pad layer formed of a salicide layer on the cell plug layer is formed with an area larger than the plug layer for simplifying the fabrication process and securing an adequate fabrication allowance, including the steps of (1) forming metal gate electrodes on a semiconductor substrate inclusive of a cell region and a peripheral circuit region, (2) forming gate sidewalls at sides of the gate electrode layers on the cell region and forming a material layer for forming a plug on an entire surface, (3) patterning the material layer for forming a plug on the peripheral circuit region, to form a resistive layer, (4) planarizing the material layer for forming a plug on the cell region, to form a plug layer which stuffs spaces between the gate electrode layers, and (5) selectively forming contact pad layers on a top of the plug layer on the cell region and a portion of the peripheral circuit region and converting into silicide.