The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2001
Filed:
Jan. 12, 1999
Jiahua Huang, San Jose, CA (US);
Pei-Yuan Gao, San Jose, CA (US);
Anne E. Sanderfer, Campbell, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is removed, the surface of the layer of interlayer dielectric is lowered below the tops of metal plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized to the surface of the layer of interlayer dielectric and the metal layer is reformed on the surface of the interlayer dielectric. If the metal layer is determined to be good, the metal layer is etched. If the metal etch is faulty, the metal layer is removed, the layer of interlayer dielectric is reduced to below the tops of plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized down to the surface of the layer of interlayer dielectric and the layer of metal is reformed.