The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2001

Filed:

Oct. 13, 1998
Applicant:
Inventor:

Dahcheng Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ; H01L 2/18234 ; H01L 2/120 ;
U.S. Cl.
CPC ...
H01L 2/18242 ; H01L 2/18234 ; H01L 2/120 ;
Abstract

A method for manufacturing a bottom storage node of a stack capacitor on a substrate is disclosed. The method comprises the steps of: (1) forming a first dielectric layer onto said substrate; (2) forming a nitride layer onto said first dielectric layer; (3) patterning and etching said first dielectric layer and said nitride layer until said substrate is reached, to form a contact opening; (4) forming a first conducting layer into said contact opening and atop said nitride layer; (5) removing a portion of said first conducting layer atop said first dielectric layer to form a plug in said contact opening; (6) forming a second dielectric layer atop said nitride layer and said plug; (7) patterning and etching said second dielectric layer to form a trench above said plug; (8) forming an amorphous polysilicon layer into said trench and atop said second dielectric layer; (9) removing a portion of said amorphous polysilicon layer atop said second dielectric layer; (10) removing remaining portion of said second dielectric layer; and (11) forming an HSG polysilicon layer atop said amorphous polysilicon layer.


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