The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2001
Filed:
Oct. 22, 1999
Wen-Kuan Yeh, Chu-Pei, TW;
Wen-Jeng Lin, Pan-Chiao, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method for forming combining a logic circuit and a capacitor of a passive element is disclosed. The method includes the following steps. First, a semiconductor wafer having a first dielectric layer and a first contact is provided. A first metal layer is formed on the first contact and around an estimated area. A second dielectric layer is formed on the first metal layer and the first dielectric layer. The second dielectric layer is formed on the first metal layer and the first dielectric layer. The second metal is formed on areas of the metal layer of the estimated areas. The third dielectric layer is formed on the second metal layer and the second dielectric layer. The fourth dielectric layer is formed on the third dielectric layer. The fifth dielectric layer is formed on the fourth dielectric layer. Sequentially the fifth dielectric layer, the fourth dielectric layer, the third dielectric layer, and the second dielectric layer are all etched.