The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2001
Filed:
Oct. 20, 1999
Benjamin Szu-Min Lin, Hsin-Chu, TW;
Jung-Chao Chiou, Hsin-Chu, TW;
Chin-Hui Lee, Taipei, TW;
Chuan-Fu Wang, San-Chung, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole. Finally, a spacer is formed using an insulating material on the walls of the node contact hole to complete the node contact hole. The spacer completely covers the walls of the two bit lines within the node contact hole but the surface of the silicon substrate exposed at the bottom of the node contact hole is not completely covered by the spacer.