The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Jul. 15, 1998
Shigeki Takizawa, Meiwa-mura, JP;
Advantest Corp, Tokyo, JP;
Abstract
A semiconductor test system having a high repetition rate and small jitter clock generator for supplying the clock signal to a device under test (DUT). The semiconductor test system includes a clock generator for generating a reference clock signal, a frame processor for producing a clock signal of predetermined waveform based on the reference clock signal from the clock generator, a phase lock loop (PLL) circuit for generating a clock signal based on the clock signal from the frame processor where the frequency generated by the PLL circuit is higher than that of the clock signal from the frame processor, and a driver for directly receiving the clock signal from the PLL circuit to apply the clock signal to the DUT with a predetermined amplitude.