The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2001

Filed:

Feb. 24, 1999
Applicant:
Inventors:

Karsten Wieczorek, Reichenberg-Boxdorf, DE;

Nick Kepler, Saratoga, CA (US);

Paul R. Besser, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/131 ; H01L 2/1469 ; H01L 2/144 ; H01L 2/13205 ;
U.S. Cl.
CPC ...
H01L 2/131 ; H01L 2/1469 ; H01L 2/144 ; H01L 2/13205 ;
Abstract

A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process due to grain boundary induced stress induced junction spiking amorphizes the metal layer prior to annealing during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, dopant or non-dopant material is implanted into the anamorphous metal layer that has been previously deposited over the gate and source/drain junctions. The ion implantation is performed at an energy level sufficient to amorphize the metal (e.g. cobalt), and substantially eliminate grain boundaries in the metal and release grain boundary induced stress. This prevents grain boundary stress induced diffusion of the metal during the first phase of the silicidation process, where the metal is the diffusing species. The silicide regions that are formed during subsequent annealing steps therefore do not exhibit junction spikes.


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