The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Jun. 04, 1999
Jenn Ming Huang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-chu, TW;
Abstract
A method for fabricating high-aspect-ratio contacts on integrated circuits, such as embedded DRAMs, using a borderless pre-opened hard-mask technique is achieved. After forming gate electrodes for field effect transistors (FETs) and local interconnections from a polycide layer having a silicon nitride (Si,N,) hard mask or cap layer, an anti-reflective coating is used to protect the FET source/drain areas. A photoresist mask and plasma etching are used to remove portions of the hard mask on the interconnections for contact openings, while the anti-reflective protects the source/drain areas. The photoresist mask and the anti-reflective coating are removed, and an interlevel dielectric (ILD) layer is deposited. The high-aspect-ratio contact openings can now be etched in the ILD layer to the source/drain areas, while concurrently etching reliable contact openings to the polycide interconnections where the cap Si,N,has been removed without overetching the source/drain areas.