The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2001
Filed:
Apr. 25, 2000
Chia-Hsin Hou, Hsinchu Hsien, TW;
Jyh-Kuang Lin, Hsinchu, TW;
Tz-Guei Jung, Hsinchu, TW;
Joe Ko, Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method for fabricating a capacitor is applicable to a fabrication process for a mixed circuit. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.