The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2001

Filed:

Nov. 18, 1999
Applicant:
Inventors:

Lawrence Clevenger, LaGrangeville, NY (US);

Greg Costrini, Hopewell Junction, NY (US);

Dave Dobuzinsky, Hopewell Junction, NY (US);

Yoichi Otani, Wappingers Fall, NY (US);

Thomas Rupp, Stormville, NY (US);

Viraj Sardesai, Poughkeepsie, NY (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ; G01L 2/130 ;
U.S. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ; G01L 2/130 ;
Abstract

A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C,F,, 20-80 sccm of CO, 2-30 sccm of O,and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.


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