The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2001

Filed:

May. 18, 1998
Applicant:
Inventors:

Rina Chowdhury, Austin, TX (US);

Ajay Jain, Austin, TX (US);

Olubunmi Adetutu, Austin, TX (US);

Assignee:

Motorola Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A method for forming a copper interconnect begins by depositing a barrier layer (,) within an in-laid region (,). An edge exclusion protection layer (,) is formed over the barrier layer (,), and this layer (,) is processed so that it only lies within the edge exclusion region (,) of the wafer. The layer (,) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (,) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (,). The layer (,) is not formed in an edge exclusion region (,). Electroplating is then used to thicken the copper material to form a copper layer (,) over the layer (,) wherein the in-laid copper interconnect is completed.


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