The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2001
Filed:
Nov. 24, 1998
Applicant:
Inventors:
Sunil D. Mehta, San Jose, CA (US);
Xiao-Yu Li, San Jose, CA (US);
Assignee:
Vantis Corporation, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/14763 ;
Abstract
A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface.