The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2001
Filed:
Nov. 15, 1999
Jerald N. Hall, Scappoose, OR (US);
Orville H. Christeson, Hillsboro, OR (US);
Mike Kinion, Hillsboro, OR (US);
Sean R. Babcock, Portland, OR (US);
Frank L. Wildgrube, Hillsboro, OR (US);
Frank E. LeClerg, Hillsboro, OR (US);
John Yuratovac, Rancho Cucamonga, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio. The bus, coupled to the programmable multiplexer, the processor and the storage medium, operates to provide instructions and data to the processor, including the BIOS, in a speed consistent with the asserted bus/core ratio.