Built-in self-test unit having a reconfigurable data retention test

Abstract

An integrated circuit device is disclosed having a BIST Uinit with recolfiLgurable data retention testing for a memory array. In one embodiment, the integrated circuit device includes a memory array, a BIST unit, an externally-programmable pause count register, and a pause counter. The BIST unit is configured to apply a test pattern of memory accesses to the memory array. The test pattern preferably includes a first phase for writing data values to the memory array, a second phase for stressing the memory array, and a third phase for verifying the data values after the array has been stressed. The length of the second phase is determined by the count stored in the externally-programmable register. The count may be loaded into the pause counter by the BIST prior to the second phase. In the second phase, the BIST unit asserts a pause signal which causes the pause counter to suppress the clock signal to the BIST unit during the second phase, thereby suspending the BIST unit's activity. The pause signal may also initiate “disturbances” to the memory array during the second phase, such as degrading the power supply voltage and initiating the activity of a sub-BIST unit that conducts memory accesses near a target memory location designed to “stress” that target memory location. Once the pause counter finishes counting, the clock signal to the BIST unit is re-established, allowing the BIST unit to conduct the verification phase.