The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2001

Filed:

Dec. 09, 1999
Applicant:
Inventors:

Chih-Yuan Hsiao, Feng-Shan, TW;

Hua-Chou Tseng, Hsin Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

The present invention relates to a method of forming a MOS transistor on a semiconductor wafer. A gate is first formed on the silicon substrate of the semiconductor wafer, then a first spacer made of silicon nitride and the LDD are formed adjacent to the gate. A conductive layer is formed on the semiconductor wafer that forms a corner on the conjoining section of the spacer and the silicon substrate. A spacer made of silicon oxide is formed on the corner of the conductive layer,, then an etching process is performed to remove the conductive layer above the gate and the silicon substrate. The conductive layer on the corner adjacent to the first spacer remains. Finally, the spacer made of silicon oxide is completely removed, and an ion implantation process is performed to form a source and drain on the silicon substrate adjacent to the conductive layer.


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