The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2001
Filed:
Feb. 18, 1999
Jenn Ming Huang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method for a self-aligned contact (SAC) that forms top and bottom spacers on the sidewalls of the interlevel dielectric layer. Spaced gate structures are formed between said spaced isolation regions. The gate structure is comprised of a gate oxide layer; a conductive layer; a cap layer. Lightly doped drain regions (LDD) are formed. An interlevel dielectric (ILD) layer is formed. A contact hole is etched that exposes the LDD region between the gate structures and removes a portion of the cap layer. An interlevel dielectric spacer layer is formed over the interlevel dielectric layer, the sidewalls of the contact hole and on the LDD region. In a key step, the interlevel dielectric spacer layer is anisotropically etched forming a top spacer on the sidewalls of the upper opening and a bottom spacer on the lower opening. A contact plug is formed to fill the contact hole and electrically contacting the LDD region. The invention also forms borderless contact hole spacers. The invention's IDL spacers can be thinner than conventional spacers and allow better gap filling for the contact plug.