The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2001
Filed:
May. 24, 1999
Chaochieh Tsai, Taichung, TW;
Kuan-Yao Wang, Tainan, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method of fabricating a CMOS device having (1) an anti-SCE block region below a channel region and (2) a metal gate. The invention uses a masking layer having an opening to define the anti-SCE block implant and also the gate structure. The method comprises forming a masking layer having a first opening defining a channel region over the substrate. In a key step, performing an Anti-SCE block implant to create an anti-SCE region. Next, a forming a gate dielectric layer is formed on the substrate in the first opening. A conductive layer is formed over the substrate in the channel region and over the masking layer. The conductive layer is planarized to form a metal gate metal. The barrier layer is removed. LDD regions are formed. Spacers are formed on the sidewall of the metal gate. Source/Drain regions are implanted adjacent to the metal gate stack.