The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2001

Filed:

Jun. 05, 1997
Applicant:
Inventors:

Chok J. Chia, Cupertino, CA (US);

Seng-Sooi Lim, San Jose, CA (US);

Maniam Alagaratnam, Cupertino, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/304 ; H01L 2/334 ;
U.S. Cl.
CPC ...
H01L 2/304 ; H01L 2/334 ;
Abstract

One aspect of the invention relates to a flip-chip semiconductor package. In one version of the invention, the flip-chip semiconductor package includes a package substrate having an upper surface, a lower surface and a plurality of conductive traces, the upper surface having an upper plurality of electrical contacts coupled to the conductive traces, the lower surface having a lower plurality of electrical contacts coupled to the conductive traces, the lower plurality of electrical contacts being attachable to electrical contacts on a printed circuit board; a semiconductor die having an active surface and a non-active surface, the active surface having a plurality of circuit elements and a plurality of bond pads formed thereon, the bond pads being attached to the upper plurality of electrical contacts by solder bumps, the non-active surface having a plurality of grooves formed thereon; and a heat sink attached to the non-active surface of the semiconductor die.


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